ModelSim / Questa Core: HDL Simulation
ModelSim /Questa Core: HDL Simulation teaches users new to using ModelSim or Questa SIM for HDL simulation.
You will learn how to effectively use ModelSim/Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs.
CONTENT I GOALS
Support of HDL behavioral simulations
Basic concepts in the digital design flow
Introduction on how to invoke the Visualizer debug environment
Hands-on lab exercises
THE TRAINER
Alexandru Vlad Velea
has an Electronics, Telecommunications and Information Technology University degree followed by MBA postgraduate degree.
From 2005 on he has been covering mostly the following Siemens products:
- HDL design, simulation and synthesis
- Wiring and harness design
He has a bright knowledge as consultant/ advisor/ technical support/ tools trainer. He is Wiring Harness consultant/ advisor for the Mentor Graphics / Siemens tools since 2011 and Digital IC flow (design/ simulation/ synthesis) consultant/ advisor for the Mentor Graphics/ Siemens tools starting 2005.
We are an Expert Partner of Siemens Digital Industries Software. Siemens Digital Industries Software awards the status "Expert" to sales partners who have in-depth expert knowledge in a product area or industry and have proven this repeatedly in reference projects.
Alexandru Vlad Velea is certified by Siemens for the products Capital | Capital Essentials (formerly VeSys®) for the automotive and aerospace (Aero) markets and continuously undergoes a mandatory certification program to verify and expand his competencies.
We reserve the right to use another qualified trainer.
Requirements: Some VHDL or Verilog knowledge I Some familiarity with digital design concept I Duration: 1 day I Language: English / optional German I Price: upon request
More information
Dates
upon request
We are happy to offer further options such as live online sessions and on-site training upon request.
Our Headquarter
Cadlog Group S.r.l.
Via Derna, 26
20132 Milano - Italy
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