Assertion Based Verification tackles the limitations of today’s verification flows. It improves observability in simulation and provides targets for formal verification, increasing controllability. In addition, assertions facilitate design reuse through self-checking code.
This webinar introduces you to the concept of Assertion Based Verification and shows you the tools to start using the techniques in your design and verification tasks. You will learn what OVL, PSL and SVA means, how you can write assertions for your code, and how you can simulate with the assertions using ModelSim/Questa and its assertion capabilities. You will also be introduced to the Assertion Thread Viewer, and its use in debugging assertion issues.
What You Will Learn
- What Assertion Based Verification is
- What OVL, PSL and SVA are
- How to simulate assertions using ModelSim/Questa
- How to use the Assertion Thread Viewer
A background in Microelectronics, Physics, and more than 19 years of EDA experience. Rachid Laaris entered the Electronic Design Automation (EDA) in 1998 as an application engineer and continued his career to consultancy in signal integrity on behalf of European companies.
As part of the Cadlog team, he is dedicated to delivering productive engineering and HDL development solutions to customers via the best in class software and support for tomorrow’s complex designs.