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Questa Verification IP

An integral part of the Enterprise Verification Platform from Siemens Digital Industries Software

Today’s designs rely heavily on a growing variety of complex industry-standard interface protocols. Questa Verification IP (QVIP) enables engineers to effectively deal with this complexity, by providing checks to ensure protocol compliance, providing a comprehensive compliance test suite, and including the ability to collect and analyze coverage

Questa Verification IP (QVIP) frees engineers from spending time developing BFMs, verification components, or VIP, so they can focus on the unique and high-value aspects of their designs.

Large library of protocols and memory models in Questa Verification IP

Questa Verification IP supports a large library of industry-standard protocol and memory inter- faces and devices. It includes standard SystemVerilog UVM components using a consistent, common architecture that allows rapid deployment and sharing of multiple protocols and memory models within a verification team. Test plans, compliance tests, test sequences, and protocol coverage are all included as SystemVerilog and XML source code, allowing easy reuse, extension, and debug. All QVIP components include a comprehensive set of protocol checks, error injection, and debug capabilities.

Formats supported by Questa Verification IP

The Questa Verification IP library of reusable components supports many industry-standard interfaces:

Questa Verification IP Library

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Questa Verification IP

Download the brochure to know how QVIP ensures maximum productivity and flexibility for the verification of block-level, subsystem, and SoC designs.

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