FPGA Design Verification with Questa Prime

The Questa Advanced Simulator for FPGA Design Verification achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms of SystemVerilog and VHDL, improving SystemVerilog and mixed VHDL/SystemVerilog RTL simulation performance by up to 10X. Questa also supports very fast time-to-next simulation and effective library management while maintaining high performance with unique capabilities to pre-optimize and define debug visibility on a block by block basis enabling dramatic regression throughput improvements of up to 3X when running a large suite of tests.

To increase simulation performance for large designs with long simulation times, Questa also has a Multi-Core option. Questa Multi-Core takes advantage of modern computing systems by partitioning the design to run in parallel on multiple CPUs or computers using either automatic or manually driven partitions. To achieve even greater performance, Questa supports TBX; the highest performance Transaction Level link to the Veloce platform enabling a 100x increase in performance with debug visibility and a common testbench.