A fully automatic formal bug hunting app that finds bugs due to common RTL coding errors
Questa AutoCheck helps you to find bugs early in your design. It automatically generates properties to support an ever-growing variety of static and dynamic checks such as dead code analysis, finite state machine deadlock, combinatorial loops, and liveness; covering common design errors and unimagined corner cases.
This paper seeks to take the mystery out of the use of formal methods for hardware verification. In this discussion, we will first explain formal methods as clearly and concisely as possible. We will then look at the state of the industry and the changes over the last decade or so that have enabled the widespread use of formal methods for hardware verification. With this knowledge in-hand, we will examine and explain the contents of DO-254 Appendix B 3.3.3 “Formal Methods.” Finally, we will bring this information together and provide recommendations for using formal methods on a DO- 254 project.
Questa AutoCheck Benefits
Easy-to-use, push-button bug hunting
- No knowledge of formal or ABV is required!
- Automatic assertion creation eliminates the need to write assertions
- Leverages the common Questa Visualizer debug platform
Finds bugs early in the design cycle
- Users can start verifying as soon as RTL code is written or changed
- No testbench or assertions are necessary!
- Users don’t have to bother writing simple tests
Automatically improves design quality
- Explores sequential design behavior to find corner-case bugs that will be missed by lint
- Finds common functional design issues in registers, FSMs, buses, and memories
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Tools for Simulation and Verification
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