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From ModelSim to Questa, your path to success

Online event: Webinar - 14th of December - 11h00

Overview

This webinar will go through the simulation options to better understand the differences between the ModelSim and Questa simulators and will describe the various productivity flows available in Questa, it will also introduce the advanced techniques and methodology necessary for the design and verification of high-end FPGA and ASIC.

What you will learn

  • Differences between ModelSim and Questa simulators
  • Productivity flows available in Questa
  • Verification techniques of high-end FPGA and ASIC




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Highly Productive

Highly productive advanced verification solution with verification management for coverage closure of large, complex electronic systems.

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Easy to Use

Easy to use, fast time-to-debug through native assertions, and a complete multi-abstraction and multi-language debug environment including transaction-level debug.

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Automated Test Development

Constrained-random stimulus generation to automate test development.

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Advanced Testbenches

Native advanced SystemVerilog testbench capabilities with OVM and UVM combined with unique debug function to ease the development and debug of advanced testbenches.

Discover HIGH PERFORMANCE AND CAPACITY IN FPGA DESIGN VERIFICATION

The value of our solutions is built on the experience gained next to our customers

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Siemens Solution Partner Smart Expert
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